9.3 Framed SPI modes
The module supports a very basic framed SPI protocol while operating in either master or slave modes. The following features are provided in the SPI module to support framed SPI modes:
- The control bit FRMEN (SPIxCON<14>) enables framed SPI modes and causes the SSx pin to be used as a frame synchronization pulse input or output pin,
- The control bit SPIFSD (SPIxCON<13>) determines whether the SSx pin is an input or an output, i.e. whether the module receives or generates the frame synchronization pulse.
- The frame synchronization pulse is an active high pulse for a single SPI clock cycle.
The following two framed SPI modes are supported by the SPI module:
- Frame master mode: the SPI module generates the frame synchronization pulse and provides this pulse to other devices at the SSx pin.
- Frame slave mode: the SPI module uses a frame synchronization pulse received at the SSx pin.
The framed SPI modes are supported in conjunction with the master and slave modes. The following four framed SPI configurations are available to the user: SPI master mode and frame master mode, SPI master mode and frame slave mode, SPI slave mode and frame master mode, and SPI slave mode and frame slave mode. These four modes determine whether or not the SPIx module generates the serial clock and the frame synchronization pulse. Fig. 9-7 shows block diagram of the master and slave connection in master and frame slave mode.
Fig. 9-7 Master and slave connection in master and frame slave mode
The SPI clock at the SCKx pin is controlled by the FRMEN (SPIxCON<14>) and MSTEN (SPIxCON<5>) control bits. When FRMEN (SPIxCON<14>)=1 and MSTEN (SPIxCON<5>)=1, the SCKx pin becomes an output and the SPI clock at SCKx becomes a free running clock, i.e. it will exists irrespective of whether the module is transmitting data or waiting. This mode is intended for the master devices. When FRMEN (SPIxCON<14>)=1 and MSTEN (SPIxCON<5>)=0, the SCKx pin becomes an input pin. This mode is intended for the slave devices.
The polarity of the clock pulse is selected by the CKP (SPIxCON<6>) control bit. The CKE (SPIxCON<8>) control bit is not used for the framed SPI modes and should be cleared by the user software. When CKP (SPIxCON<6>)=0, the frame synchronization pulse output and the SDOx output change on the rising edge of the clock pulses at the SCKx pin. Input data are sampled at the SDOx input pin on the falling edge of the SPI clock pulses at the SCKx pin.
When the control bit CKP (SPIxCON<6>)=1 the frame synchronization pulse output and the SDOx data output change on the falling edge of the clock pulses at the SCKx pin. Input data are sampled at the SDIx input pin on the rising edge of the SPI clock at the SCKx pin.
When the SPIFSD (SPIxCON<13>) control bit is cleared, the SPIx module is in the frame master mode of operation. In this mode the frame synchronization pulse is initiated by the module when the user software writes the transmit data to SPIxBUF location, i.e. writing the SPIxTXB register with transmit data. At the end of the frame synchronization pulse, the SPIxTXB is transferred to the SPIxSR and data transmission/reception begins.
When the SPIFSD (SPIxCON<13>) control bit is set, the module is in frame slave mode. The frame synchrinization pulse is generated by an external source. When the module samples the frame synchronization pulse, it will transfer the contents of the SPIxTXB register to the SPIxSR register and data transmission/reception begins. The user must make sure that the correct data are loaded into the SPIxBUF for transmission before the frame synchronization pulse is received.
Attention!!!
Receiving a frame synchronization pulse will start a transmission, regardless of whether data were written to SPIxBUF. If no write was performed, the old contents of SPIxBUF will be transmitted.
9.3.1 SPI module in master mode and frame master mode
This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) and FRMEN (SPIxCON<14>) bits to ‘1’ and SPIFSD (SPIxCON<13>) bit to ‘0’. In this mode, the serial clock will be output continuously at the SCKx pin, regardless of whether the module is transmitting. When the SPIxBUF is written, the SSx pin will be driven high on the next transmit edge of the SCKx clock (active edge depends on the control bit CKP). The SSx pin will be high for one SCKx clock cycle. The module will start transmitting data on the next transmit edge of the SCKx, as shown in Fig. 9-8. The connection of master and slave is shown in Fig. 9-7.
Fig. 9-8 Waveforms of the SPI module in master mode and frame master mode
9.3.2 SPI module in master mode and frame slave mode
This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>), FRMEN (SPIxCON<14>), and SPIFSD (SPIxCON<13>) bits to ‘1’. The SSx pin is an input, and it is sampled on the sample edge of the SPI clock. When it is sampled high, data will be transmitted on the subsequent transmit edge (controlled by the CKP bit) of the SPI clock. When the transmission is completed, the interrupt flag SPIxIF is generated by the SPIxSR register. The user must make sure that the correct data are loaded into the SPIxBUF for transmission before the signal is received at the SSx pin. Fig. 9-9 shows the waveforms of the SPI module in master mode and frame slave mode. Connection diagram of the module in master mode and frame slave mode is showm in Fig. 9-10.
Fig. 9-9 Waveforms of the SPI module in master mode and frame slave mode
Fig. 9-10 Connection diagram of the module in master mode and frame slave mode
9.3.3 SPI module in slave mode and frame master mode
This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) bit to ‘0’, FRMEN (SPIxCON<14>) bit to ‘1’, and SPIFSD (SPIxCON<13>) bit to ‘0’. The input SPI clock will be continuous at the SCKx pin in slave mode. The SSx pin will be an output when the SPIFSD (SPIxCON<13>) bit is cleared. Therefore, when the SPIxBUF is written, the module will drive the SSx pin high on the next transmit edge of the SPI clock. The SSx pin will be driven high for one SPI clock cycle. Data will start transmitting on the next SPI clock falling edge. A connection diagram for this operating mode is shown in Fig. 9-11
Fig. 9-11 Connection diagram of the module in slave mode and frame master mode
9.3.4 SPI module in slave mode and frame slave mode
This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) bit to ‘0’, FRMEN (SPIxCON<14>) bit to ‘1’, and SPIFSD (SPIxCON<13>) bit to ‘1’. Therefore, both the SCKx and SSx pins will be the inputs. The SSx pin will be sampled on the sampling edge of the SPI clock (in the middle of the SPI cycle). When SSx is sampled high, data will be transmitted on the next transmit edge of SCKx (controlled by the CKP bit). A connection diagram for this mode of operation is shown in Fig. 9-12.
Fig. 9-12 Connection diagram of the module for slave mode and slave frame mode