In the master mode, the clock provided to the SPI module is the instruction cycle TCY . This clock will then be prescaled by the primary prescaler, specified by PPRE<1:0> (SPIxCON<1:0>), and the secondary prescaler, specified by SPRE<2:0> (SPIxCON<4:2>). The prescaled instruction clock becomes the serial clock and is provided to external devices via the SCKx pin.
FCY = 30 MHZ | SECONDARY PRESCALER SETTINGS | |||||
---|---|---|---|---|---|---|
1:1 | 2:1 | 4:1 | 6:1 | 8:1 | ||
Primary prescaler settings | ||||||
1:1 | 30 000 | 15 000 | 7 500 | 5 000 | 3 750 | |
4:1 | 7 500 | 3 750 | 1 875 | 1 250 | 938 | |
16:1 | 1 875 | 938 | 469 | 313 | 234 | |
64:1 | 469 | 234 | 117 | 78 | 59 | |
FCY = 5 MHZ | ||||||
Primary prescaler settings | ||||||
1:1 | 5 000 | 2 500 | 1 250 | 833 | 625 | |
4:1 | 1 250 | 625 | 313 | 208 | 156 | |
16:1 | 313 | 156 | 78 | 52 | 39 | |
64:1 | 78 | 39 | 20 | 13 | 10 |
NOTE: SCKx clock frequencies shown in kHz. All frequencies are not supported; electrical characteristics of individual microcontrollers of dsPIC30F family should be consulted.
program SPITest; const CS_PIN = 0; // DAC CS pin var value : word; procedure InitMain(); begin TRISF.CS_PIN := 0; // CS pin LATF.CS_PIN := 1; // Set CS to inactive Spi1_Init_Advanced(_SPI_MASTER, _SPI_16_BIT, _SPI_PRESCALE_SEC_1, _SPI_PRESCALE_PRI_1,_SPI_SS_DISABLE, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_HIGH,_SPI_ACTIVE_2_IDLE); // Init SPI end; // DAC increments (0..4095) --> output voltage (0..Vref) procedure DAC_Output(valueDAC : word) ; begin while (SPI1STAT.1 = 1) do // wait for SPI module to finish, if doing something nop; LATF.CS_PIN := 0; // CS enable for DAC SPI1BUF := 0x3000 or valueDAC; // Write CurrentValue to DAC (0x3 is required by DAC) while (SPI1STAT.1 = 1) do // Wait for SPI module to finish write nop; LATF.CS_PIN := 1; // CS disable for DAC end; begin InitMain(); while 1 = 1 do begin value := 1; while value < $FFF do begin DAC_Output(value); Delay_ms(5); value := value+1; end; end; // the output in the mid-range end.Procedure Spi2_Init initializes the SPI module in master mode 8-bit formatted, without the SS2 pin, sampling in the middle of the SPI cycle, prescale 1:8, and the clock FCY:1 low while waiting. If another format or communication speed is desired, the procedure Spi2_Init_Advanced instead of Spi2_Init should be used. The procedure Spi2_Data_Ready reads the value of the status bit SPIRBF (SPI2STAT<0>) and checks if there are data loaded into the receive buffer register. The procedure Spi2_Write transmits data via the SPI module. Data reception is performed by the procedure Spi2_Read. The SPI moduled is disabled by the procedure Spi2_Stop (clearing the control bit SPIEN), and the SPI module enable (setting the control bit SPIEN) is performed automatically by the procedure Spi2_Init or Spi2_Init_Advanced.